Virtual Labs

a: The Q output is either SET or RESET as soon as the D input goes HIGH or LOW b: The output complement follows the input when enabled c: Only one of the inputs can be HIGH at a time d: The output toggles if one of the inputs is held HIGH

a: AND or OR gates b: Ex-OR or Ex-NOR gates c: NOR or NAND gates d: AND or NOR gate

a: 1 b: 2 c: 3 d: 4

a: S-R, J-K, D b: S-R, J-K, T c: J-K, D, S-R d: J-K, D, T

a: S-R flip-flop b: S-R latch c: D latch d: D flip-flop

Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates